1. Technical Field
This disclosure relates to memories, and more particularly to collision prevention in a memory.
2. Description of the Related Art
Many devices use memory arrays that include dual port bit cells in which the bit cells have separate read and write wordlines and separate read bitlines and write bitlines to allow for simultaneous read and write access to both the read and write ports, as long as the read is specified on a different address than the write. This is particularly true in memories used as register files. However, when the read and write address are the same, a collision would result if both the read and write are allowed to proceed. These collisions can be problematic for a variety of reasons. For example, the time it takes a bit cell to recover from a write operation may increase significantly due to the write operation trying to overwrite opposite data being read out. In addition, collisions may cause additional current drain, as well as erroneous data being read from or written to the affected bit cell.
Accordingly, there are conventional mechanisms to prevent these collisions. One such mechanism uses comparators to detect the same address up front. This type of address detection may require many exclusive-OR (XOR) gates and a “tree” of NAND/NOR gates to combine the many address bits into a single “collision” signal to stop a given wordline from being activated and causing slow write behavior. This conventional approach can be slow, and requires many more gates. In addition, some bit cells may be designed to withstand the contention that arises from a collision. More particularly, another conventional approach increases the size of the n-type pulldown transistors to be greater than the sum of the wordline pass transistors. This is not considered to be an optimal approach.